Heterogeneous programming with SYCL Logo
  • Setting up your system

The lesson

  • What is SYCL?
  • Device discovery
  • Queues, command groups, and kernels
  • Data management with buffers and accessors
  • Data management with unified shared memory
  • Expressing parallelism with SYCL: basic data-parallel kernels
  • Expressing parallelism with SYCL: nd-range data-parallel kernels
  • The task graph: data, dependencies, synchronization
  • Heat equation mini-app
  • Using sub-groups in SYCL
  • Profiling SYCL applications
  • Buffer-accessor model vs unified shared memory

Reference

  • Quick Reference
  • Bibliography
  • Instructor’s guide
Heterogeneous programming with SYCL
  • Index
  • Edit on GitHub

Index

C | F | Q | R | S | U | V

C

  • class template argument deduction
  • CTAD

F

  • field-programmable gate array
  • FPGA

Q

  • queue
  • queues

R

  • RAII
  • resource acquisition is initialization

S

  • selector
  • selectors
  • standard template library
  • STL

U

  • unified shared memory
  • USM

V

  • vector engines

© Copyright 2021, Roberto Di Remigio and individual contributors..

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