Instructor’s guide

Learning outcomes

What is SYCL and why it is useful.
Write hardware-agnostic code to express parallelism using the queue, command group, and kernel abstractions.
Use buffer and accessors to handle memory across devices.
Evaluate drawbacks and advantages of unified shared memory.
Get acquainted with the SYCL profiling API.

Prerequisites

Before attending this workshop, please make sure that you have access to a machine with the hipSYCL compiler (v0.9.2) and CMake (>=3.14) installed.

This workshop is organized in collaboration with NRIS and IT4I. We will work on the exercises using the Karolina supercomputer, a EuroHPC Joint Undertaking petascale system.

Day 1 - Tuesday 19 April 2022

9:00 - 9:10	Welcome and introduction to the training course
9:10 - 9:40	What is SYCL?
9:40 - 9:45	Break
9:45 - 10:15	Device discovery
10:15 - 10:25	Break
10:25 - 10:55	Queues, command groups, and kernels
10:55 - 11:00	Break
11:00 - 11:30	Data management with buffers and accessors
11:30 - 11:35	Break
11:35 - 12:05	Data management with unified shared memory
12:05 - 12:15	Break
12:15 - 12:30	Wrap-up

Day 2 - Wednesday 20 April 2022

9:00 - 9:10	What did we cover yesterday?
9:10 - 9:40	Expressing parallelism with SYCL: basic data-parallel kernels
9:40 - 9:50	Break
9:50 - 10:20	Expressing parallelism with SYCL: nd-range data-parallel kernels
10:20 - 10:30	Break
10:30 - 11:10	The task graph: data, dependencies, synchronization
11:10 - 11:20	Break
11:20 - 12:00	Heat equation mini-app
12:00 - 12:10	Break
12:00 - 12:30	Wrap-up

Day 3 - Wednesday 21 April 2022

9:00 - 9:10	What did we cover yesterday?
9:10 - 9:40	Using sub-groups in SYCL
9:40 - 9:50	Break
9:50 - 10:20	Profiling SYCL applications
10:20 - 10:30	Break
10:30 - 11:10	Buffer-accessor model vs unified shared memory
11:10 - 11:20	Break
11:20 - 11:30	Wrap-up

Prerequisites

Before attending this workshop, please make sure that you have access to a machine with the hipSYCL compiler (v0.9.1) and CMake (>=3.14) installed.

This workshop is organized in collaboration with CSC and IZUM. We will work on the exercises using the Vega supercomputer, a EuroHPC Joint Undertaking petascale system.

Day 1 - Monday 8 November 2021

9:00 - 9:10	Welcome and introduction to the training course
9:10 - 9:40	What is SYCL?
9:40 - 9:45	Break
9:45 - 10:15	Device discovery
10:15 - 10:25	Break
10:25 - 10:55	Queues, command groups, and kernels
10:55 - 11:00	Break
11:00 - 11:30	Data management with buffers and accessors
11:30 - 11:35	Break
11:35 - 12:05	Data management with unified shared memory
12:05 - 12:15	Break
12:15 - 12:30	Wrap-up

Day 2 - Tuesday 9 November 2021

9:00 - 9:10	What did we cover yesterday?
9:10 - 9:50	expressing-parallelism
9:50 - 10:00	Break
10:00 - 10:40	The task graph: data, dependencies, synchronization
10:40 - 10:50	Break
10:50 - 11:10	Heat equation mini-app
11:10 - 11:15	Break
11:15 - 11:55	Buffer-accessor model vs unified shared memory
11:55 - 12:00	Break
12:00 - 12:30	Wrap-up